As a prior art, a technology for reducing inductance that leads to a pop-up voltage in a power converter using a semiconductor device has been disclosed in Japanese Patent Laid-open No. 11-89247. The prior technology is a method that reduces the inductance of wiring for connecting the semiconductor device and the capacitors with a conductor board laminated by interposing an insulator between the semiconductor device and the capacitors. Thereby the wiring inductance that leads to an increase in loss at switching and the occurrence of a pop-up voltage is reduced.
Now a necessary minimum circuit composition of the power converter will be explained with reference of FIG. 6. In FIG. 6, the power converter 32 comprises a semiconductor device 30 and an electrolytic capacitor 29. It is equipped with a DC power source 31, a main circuit wiring 33a, a main circuit wiring 33b, a output wiring 34 and an induction motor 35. The semiconductor device 30 inputs a DC voltage and outputs an AC current of a variable frequency to the UVE-phase output wiring 34. The induction motor 35 is driven by a current/voltage supplied through the output wiring 34. The electrolytic capacitor 29 has the function of suppressing variations in the DC voltage due to a switching operation of the semiconductor device. Although not shown in FIG. 6, in addition to the above-mentioned electric parts, the power converter is made up of a circuit substrate for controlling the switching operation of the semiconductor device 30, a cooling fin for cooling the semiconductor device 30, a cooling fan, etc.
A minimum circuit composition of a semiconductor device which is necessary to output a UVW three-phase alternating current will be explained with reference to FIG. 7. In FIG. 7, the semiconductor device 30 comprises semiconductor switches 13a, 13b, 13c, 13d, 13e and 13f, diodes 13a′, 13b′, 13c′, 13d′, 13e′ and 13f′, semiconductor switch control terminals 24a, 24b, 24c, 24d, 24e and 24f, a positive polarity DC terminal 3, a negative polarity DC terminal 2, a U-phase output terminal 4, a V-phase output terminal 5, and a W-phase output terminal 6. The terminals 4, 5 and 6 form a set of three-phase AC terminals. A DC voltage is applied between the positive polarity terminal 3 and the negative polarity terminal 2. In order to make it easy to understand the drawing, a drive circuit for outputting an on-off signal of each semiconductor switch has been omitted in drawings.
Power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) or IGBTs (Insulated Gate Bipolar Transistors) are used in the semiconductor switches 13a through 13f. Since the power MOSFET includes a diode in terms of a device structure when the power MOSFET is used in the semiconductor switch, the semiconductor switch 13a and the diode 13a′ can be constituted by one chip.
The semiconductor switches 13a, 13c and 13e are bridge-connected with the semiconductor switches 13b, 13d and 13f, respectively.
The semiconductor device 30a applies a PWM (pulse Width Modulation) control signal voltage to the semiconductor switch control terminals 24a through 24f to control time intervals taken to turn on (open) or off (close) the bridge-connected semiconductor switches 13a through 13f. Thereby three-phase AC currents of variable frequencies/variable voltages are outputted from the three-phase AC output terminals 4, 5 and 6 to the induction motor 35. A device composition for outputting the UVW three-phase currents can be realized even by three semiconductor devices each constituted by the positive polarity terminal 3, negative polarity terminal 2, bridge-connected semiconductor switches 13a and 13b, and output terminal 6.
A wiring structure that constitutes a bridge circuit in a conventional semiconductor device is shown in FIG. 4. FIG. 4 is a perspective view showing the wiring structure in the conventional semiconductor device. In FIG. 4, reference numeral 2 designates a negative polarity DC terminal, 3 designates a positive polarity DC terminal, 4, 5 and 6 designate output terminals, 11 designates an insulator, 12a, 12b and 12c designate substrate conductor patterns, 13a and 13b designate diode and semiconductor switches, 14a, 14b, 14c, 14d and 14e designate wire interconnections. In addition, reference numeral 7 designates a radiating plate, 30 designates a semiconductor device, and 15a, 15b and 15c designate insulating boards or substrates. FIG. 4 corresponds to the case in which MOSFETs are used in the semiconductor switches and shows combinations of the semiconductor switches and diodes in the form of one part. The radiating plate 7 is made of copper, an Al—SiC alloy or the like as a material.
Although the wire interconnections 14a, 14b, 14c, 14d and 14e are illustrated four by four in FIG. 4, the number of wire interconnections varies according to specifications of the semiconductor device and the diameter of each wire interconnection, and the number of the wire interconnections is by no means limited to four. Since the semiconductor switches and wire interconnections or the like mounted on the insulating substrates 15b and 15c are similar in structure and operation to those of the insulating substrate 15a, the insulating substrate 15a will be explained below. In the following description, the negative polarity DC terminal 2 and the positive polarity DC terminal 3 indicate conductor boards that constitute them.
In FIG. 4, the substrate conductor patterns 12a, 12b, and 12c are formed on the insulating substrate 15a, and the semiconductor switches 13a and 13b are respectively implemented on the substrate conductor patterns 12a and 12b. The insulating substrate 15a electrically insulates the conductor patterns formed on the insulating substrate from the radiating plate 7. The wire interconnections 14a connect the positive polarity DC terminal 3 and the substrate conductor pattern 12a, the wire interconnections 14b connect the semiconductor switch 13a and the substrate conductor pattern 12b, the wire interconnections 14c connect the semiconductor switch 13b and the substrate conductor patterns 12c, the wire interconnections 14d connect the negative polarity DC terminal 2 and the substrate conductor pattern 12c, and the wire interconnections 14e connect the output terminal 4 and the substrate conductor pattern 12b. 
When the semiconductor switches 13a and 13b performs switching from on to off in the semiconductor device 30, a current value greatly changes in a path constituted by wiring for bridge-connecting the semiconductor switches switched from on to off, wiring connected to an electrolytic capacitor and the DC terminals of the semiconductor device 30, the negative polarity DC terminal 2 and positive polarity DC terminal 3, and the electrolytic capacitor. The wiring for bridge-connecting the semiconductor switches correspond to the substrate conductor patterns 12a, 12b and 12c and the wire interconnections 14a, 14b, 14c and 14d in FIG. 4. A voltage exceeding the voltage of the electrolytic capacitor is momentarily applied to the corresponding semiconductor switch switched from on to off. The voltage (hereinafter called pop-up voltage) exceeding the electrolytic capacitor voltage is determined by the product of the total inductance of the path and electrolytic capacitor and a time-differentiated value of the current flowing through the path. When the pop-up voltage increases and the voltage applied to the corresponding semiconductor switch switched from on to off exceeds a device withstand voltage, an electrical breakdown occurs.
Thus, there is a need to suppress the pop-up voltage for the purpose of the normal operation of the semiconductor device. Since, however, the time-differentiated value of the current flowing through the path also increases with a substantial increase in current of the semiconductor device, a reduction in inductance becomes important.
A countermeasure for using each semiconductor switch high in withstand voltage is taken to cope with a problem about the pop-up voltage. When, however, the withstand voltage is increased, the semiconductor switch has a tendency that the resistance value in its on-state becomes large. Particularly, a system in which a power supply voltage is low and a large current flows in each semiconductor switch causes a problem that a loss at the semiconductor switch increases. Suppressing the pop-up voltage with the reduction in inductance makes it possible to use a semiconductor switch low in withstand voltage. Thus, large merits to the problem about the pop-up voltage, such as suppression of a rise in temperature by a reduction in the generated heat, improvements in life and reliability, or a reduction in cooling cost, etc. as its effects are brought about.